1. Field of the Invention
Embodiments of the invention relate to secure execution environments. More particularly, embodiments of the invention relate to avoiding deadlock conditions in multi-processor systems having at least one processor executing in a secure execution mode.
2. Background
Multiple processor systems are ubiquitous in today's information driven society. In some cases, it is desirable to permit one processor in the system to process security sensitive information while restricting access to that information by other processors in the system. To that end, various secure environments have been established to authenticate a potential accessor of secure data and to prevent other agents from accessing that data while exposed in a shared memory or other shared resource. In some cases, the arbitrator on the shared bus is prevented from granting the bus to any processor not executing in the secure mode. Unfortunately, some global operations, such as a stop clock operation, require an acknowledgement from all processors to indicate they are prepared for the stop clock operation to occur. When the arbitrator is holding all bus agents off the bus except for the processor in a secured mode, the remaining bus agents are unable to acknowledge the stop clock request and therefore, the stop clock operation never occurs. This results in significant power inefficiency, and/or deadlock conditions.